1. Field of the Invention
The present invention relates generally to semiconductor integrated circuit technology and more particularly to split gate memory cells used in flash EPROMs (Electrically Erasable Programmable Read Only Memory).
2. Description of Prior Art
Increased performance in computers is often directly related to a higher level of circuit integration. Tolerances play an important role in the ability to shrink dimensions on a chip. Self-alignment of components in a device serves to reduce tolerances and thus improve the packing density of chips. Other techniques can be important in shrinking device size. A method is disclosed later in the embodiments of the present invention of forming a structure with self-aligned source to floating gate, wordline to floating gate and bitline contact to wordline, which allows for significant reduction in the area of the split gate flash cell.
As is well known in the art, split gate flash cells have bitlines and wordlines and bitline contacts that connect bitlines to drain regions. Bitlines and bitline contacts are traditionally insulated from wordlines by an interlevel dielectric layer. The separation between bitline contacts and wordlines must be maintained large enough so as to avoid possible shorts that could develop between adjacent bitline contacts and wordlines. Bitline contact to wordline separations are determined by the positions of bitline contact openings, which are set by a design rule. In arriving at the design rule the possibility of misalignment must be taken into account, which results in a required separation well beyond that needed to avoid development of shorts. This requirement for increased separation, arising from the need to account for unavoidable misalignment, limits the ability to decrease cell size. Self-alignment of the bitline contact to the wordline, as in the structures disclosed by the present invention, eliminates the reliability issue, allows a reduction in cell area and facilitates shrinking the cell size. Furthermore, in the structures disclosed by the present invention there is, in addition to self-aligned bitline contact to wordline, also self-alignment of source to floating gate and wordline to floating gate; allowing a further reduction in cell area and further facilitating shrinking the cell size.
A traditional method of fabricating a split gate flash memory cell is presented in FIGS. 1a–1g, where top views of the cell are presented at successive stages of the process and in FIGS. 2a–2g, which show the corresponding cross-sections. A floating gate oxide, 6, is formed on a semiconductor substrate, 2, which preferably is a silicon substrate, to a thickness of about 80 Angstroms, followed by deposition of a first polysilicon layer, 8, to a depth of about 800 Angstroms. Active regions, 10, are defined using isolating regions, such as shallow trench isolation regions, 4. This is followed by deposition of a nitride layer, which preferably is a silicon nitride layer to a depth of about 2500 Angstroms. A photoresist layer, 14, is then formed as shown in FIGS. 1b and 2b. The photoresist pattern, 14, is used in etching the silicon nitride layer to achieve the shape of region 12 of FIG. 2b. A first polysilicon etch is performed to achieve the shape of region 8 as shown in FIG. 2b, where the sloped segments of the first polysilicon layer provide improved operation of the memory cell. Details of the method to fabricate such sharp poly tips are presented in U.S. Pat. No. 6,090,668 to Lin et al., which is herein incorporated by reference. After removal of the photoresist, an second oxide layer, 16, is deposited to a thickness of about 3000 Angstroms and a CMP (chemical-mechanical polishing) step is performed. A second photoresist layer, 18, is formed and used in successively etching the silicon nitride layer and the first polysilicon layer to achieve the structure shown in FIGS. 1c and 2c. Source regions 20 are formed by a P ion implantation at energy of about 20 keV and to a dose of about 4E14 per cm2. Removal of the second photoresist layer is followed by deposition of an third oxide layer to a depth of about 500 Angstroms, which enhances the lateral diffusion of the source implant. An third oxide etching step is performed to achieve third oxide spacers, 22. A polysilicon deposition is performed to a depth of about 3000 Angstroms and a CPM step on this layer produces a second polysilicon region 24, which serves to contact the source 20. At this stage the structure is as depicted in FIGS. 1d and 2d. The traditional method proceeds with oxidation of second polysilicon, 24, to form about 200 Angstroms of fourth oxide, 26. Next the nitride layer 12 is removed, and successive etches are performed of the first polysilicon layer, 8, and floating gate first oxide layer, 6. An fifth oxide layer, 28, is grown to a depth of about 170 Angstroms. After a third polysilicon deposition, 30, to about 2000 Angstroms, the structure is as shown in FIGS. 1e and 2e. Etching the third polysilicon layer, poly spacers, 30, are formed that serve as wordlines. A drain implant is now performed that usually is an As implant at energy about 60 keV and to a dose of about 4E15 per cm2. This forms the drain regions 36. An interlevel dielectric (ILD) layer, 38, is deposited. A photoresist layer is formed and patterned so that upon etching of the IDL layer, contacts are opened to the drain regions. A-first metal deposition follows removal of the photoresist layer. Another photoresist layer is formed and patterned so that after etching first metal bitlines 34 are formed connecting to the drain regions, 36 through the first metal contact regions 32. This completes the formation of a traditional split gate flash cell, which is shown in FIGS. 1g and 2g. 
Bitlines, 34 and bitline contacts, 32 are insulated from the wordlines, 30 by an interlevel dielectric layer, 38. The minimum separation, 40, is between bitline contacts and wordlines and this separation must be maintained large enough so as to avoid possible shorts that could develop between adjacent bitline contacts and wordlines. Bitline contact to wordline separations are determined by the positions of bitline contact openings relative to wordlines and the dimensions of the openings, which are set by design rules. In arriving at the design rule the possibility of misalignment and variability in the production of contact openings must be taken into account, which results in a required minimum separation well beyond that needed to avoid development of shorts. This requirement for increased separation limits the ability to decrease cell size. Self-alignment of the bitline contact to the wordline, as in the structures disclosed by the present invention, eliminates the reliability issue, allows a reduction in cell area and facilitates shrinking the cell size.
A split-gate flash memory cell having self-aligned source line and a novel polysilicon gate tip for enhanced F—N tunneling is disclosed in U.S. Pat. No. 6,259,131 to Sung et al. In U.S. Pat. No. 6,204,126 to Hsieh et al. there is disclosed a method for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to isolation, to source and to wordline. In U.S. Pat. No. 6,242,308 to Hsieh et al. there is disclosed a method for forming a split-gate flash memory cell having a thin floating gate and a sharp polysilicon gate tip to improve the programming and erasing speed of the cell. A method for fabricating a split-gate flash memory cell utilizing step poly to improve cell performance is provided in U.S. Pat. No. 6,229,176 to Hsieh et al.